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MT8880

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### MT8880C/MT8880C-1 集成 DTMF 收发器 #### 特性 - **完整的 DTMF 发射与接收功能**：该芯片支持数字电话信号（DTMF）的发送与接收。 - **中央办公级别的质量**：确保了高质量的语音通话体验。 - **低功耗消耗**：采用 ISO2-CMOS 技术制造，提供较低的功率消耗和高可靠性。 - **微处理器接口**：具备标准的微处理器总线，与 6800 系列微处理器兼容。 - **可调节的保护时间**：允许用户根据需要调整保护时间。 - **自动音调突发模式**：内部计数器可以精确地控制音调突发的传输。 - **呼叫进程模式**：集成的呼叫进程滤波器，使得微处理器能够分析呼叫进程音。 #### 应用场景 - **信用卡系统**：在信用卡支付系统的验证过程中用于安全验证。 - **寻呼系统**：用于寻呼网络中的信号传输。 - **中继系统/移动无线电**：在无线通信系统中作为信号中继。 - **互联拨号器**：实现电话线路之间的连接与信号转换。 - **个人电脑**：在个人电脑中作为电话通信接口使用。 #### 描述 MT8880C/C-1 是一款集成 DTMF 收发器，内含呼叫进程滤波器。这款芯片采用 Mitel 的 ISO2-CMOS 技术制造，具有低功耗和高可靠性的特点。DTMF 接收部分基于业界标准的 MT8870 单片 DTMF 接收器；发射部分则采用了开关电容 D/A 转换器，以实现低失真、高精度的 DTMF 信号传输。内部计数器提供了突发模式，使得音调突发可以以精确的定时方式传输。同时，芯片还包含了一个可以由微处理器分析呼叫进程音的呼叫进程滤波器。 #### 型号差异 MT8880C-1 与 MT8880C 在功能上基本相同，不同之处在于接收部分的性能有所增强，能够接受更低的信号水平并拒绝干扰信号。 #### 封装形式 - **MT8880CE/CE-1**：20 针塑料 DIP 封装 - **MT8880CC/CC-1**：20 针陶瓷 DIP 封装 - **MT8880CS/CS-1**：20 针 SOIC 封装 - **MT8880CN/CN-1**：24 针 SSOP 封装 - **MT8880CP/CP-1**：28 针塑料 LCC 封装工作温度范围为 -40°C 至 +85°C。 #### 功能模块图该芯片包括： - **振荡电路**：用于产生稳定的时钟信号。 - **偏置电路**：保证各部件正常工作。 - **控制逻辑**：协调各个部件的工作状态。 - **数字算法与编码转换器**：处理数字信号。 - **状态寄存器**：存储芯片当前的状态信息。 - **控制寄存器 A/B**：设置工作参数。 - **接收数据寄存器**：暂存接收到的数据。 - **中断逻辑**：处理中断请求。 - **输入/输出控制**：管理数据输入与输出。 - **低频群滤波器/高频群滤波器**：分别过滤低频和高频信号。 - **拨号音滤波器**：检测拨号音信号。 #### 引脚说明 - **IN+ (非反相运算放大器输入)**：信号输入端口之一。 - **IN- (反相运算放大器输入)**：信号输入端口之一。 - **GS (增益选择)**：提供对输出频率增益的选择访问。 - 其他引脚还包括电源输入、数据总线、控制信号等。通过上述详细介绍，我们可以了解到 MT8880C/C-1 集成 DTMF 收发器不仅具备完善的 DTMF 信号处理能力，还拥有多种实用的功能特性，适用于多种应用场景，并且具备多种封装形式以适应不同的设计需求。

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MT8880C/MT8880C-1

Integrated DTMF Transceiver

Features

• Complete DTMF transmitter/receiver

• Central office quality

• Low power consumption

• Microprocessor port

• Adjustable guard time

• Automatic tone burst mode

• Call progress mode

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radio

• Interconnect dialers

• Personal computers

Description

The MT8880C/C-1 is a monolithic DTMF transceiver

with call progress filter. It is fabricated in Mitel’s

ISO

-CMOS technology, which provides low power

dissipation and high reliability. The DTMF receiver is

based upon the industry standard MT8870

monolithic DTMF receiver; the transmitter utilizes a

switched capacitor D/A converter for low distortion,

high accuracy DTMF signalling. Internal counters

provide a burst mode such that tone bursts can be

transmitted with precise timing. A call progress filter

can be selected allowing a microprocessor to

analyze call progress tones. A standard

microprocessor bus is provided and is directly

compatible with 6800 series microprocessors. The

MT8880C-1 is functionally identical to the MT8880C

except for the performance of the receiver section,

which is enhanced to accept and reject lower signal

levels.

Ordering Information

MT8880CE/CE-1 20 Pin Plastic DIP

MT8880CC/CC-1 20 Pin Ceramic DIP

MT8880CS/CS-1 20 Pin SOIC

MT8880CN/CN-1 24 Pin SSOP

MT8880CP/CP-1 28 Pin Plastic LCC

-40°C to +85°C

Figure 1 - Functional Block Diagram

TONE

IN+

IN-

OSC1

OSC2

Ref

ESt St/GT

IRQ

/CP

Φ2

R/W

RS0

∑

D/A

Converters

Row and

Column

Counters

Transmit Data

Data

Bus

Buffer

Tone Burst

Gating Cct.

Oscillator

Circuit

Bias

Circuit

Control

Logic

Digital

Algorithm

and Code

Converter

Control

Logic

Steering

Logic

Status

Control

Receive Data

Interrupt

Logic

I/O

Control

Low Group

Filter

High Group

Filter

Dial

Tone

Filter

ISSUE 2 May 1995

ISO

-CMOS

MT8880C/MT8880C-1 ISO

-CMOS

4-34

Figure 2 - Pin Connections

Pin Description

Pin #

Name Description

20 24 28

1 1 1 IN+ Non-inverting op-amp input.

2 2 2 IN- Inverting op-amp input.

334 GSGain Select. Gives access to output of front end differential amplifier for connection of

feedback resistor.

446V

Ref

Reference Voltage output, nominally V

/2 is used to bias inputs at mid-rail (see Fig. 13).

557V

Ground input (0V).

6 6 8 OSC1 DTMF clock/oscillator input.

7 7 9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the

internal oscillator circuit. Leave open circuit when OSC1 is clock input.

81012TONETone output (DTMF or single tone).

91113R/W

Read/Write input. Controls the direction of data transfer to and from the MPU and the

transceiver registers. TTL compatible.

10 12 14 CS

Chip Select, TTL input (CS=0 to select the chip).

11 13 15 RS0 Register Select input. See register decode table. TTL compatible.

12 14 17 Φ2 System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the

device is not being accessed.

13 15 18 IRQ

Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has

been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal

representative of the input signal applied at the input op-amp. The input signal must be within

the bandwidth limits of the call progress filter. See Figure 8.

14-

18-

19-

D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS

= 1 or Φ2 is low.

18 22 26 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid

tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to

a logic low.

19 23 27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V

TSt

detected at St

causes the device to register the detected tone pair and update the output latch. A voltage

less than V

TSt

frees the device to accept a new tone pair. The GT output acts to reset the

external steering time-constant; its state is a function of ESt and the voltage on St.

20 24 28 V

Positive power supply input (+5V typical).

8,9

16,

3,5,

10,

11,

16,

23-

NC No Connection.

IN+

IN-

VRef

VSS

OSC1

OSC2

TONE

R/W

VDD

St/GT

ESt

IRQ

/CP

Φ2

RS0

20 PIN CERDIP/PLASTIC DIP/SOIC

28 PIN PLCC

•

VRef

VSS

OSC1

OSC2

IN+

IN-

VRef

VSS

OSC1

OSC2

TONE

R/W

VDD

St/GT

ESt

IRQ

/CP

Φ2

RS0

24 PIN SSOP

ISO

-CMOS MT8880C/MT8880C-1

4-35

Functional Description

The MT8880C/C-1 Integrated DTMF Transceiver

architecture consists of a high performance DTMF

receiver with internal gain setting amplifier and a

DTMF generator which employs a burst counter such

that precise tone bursts and pauses can be

synthesized. A call progress mode can be selected

such that frequencies within the specified passband

can be detected. A standard microprocessor

interface allows access to an internal status register,

two control registers and two data registers.

Input Configuration

The input arrangement of the MT8880C/C-1 provides

a differential-input operational amplifier as well as a

bias source (V

Ref

) which is used to bias the inputs at

/2. Provision is made for connection of a

feedback resistor to the op-amp output (GS) for

adjustment of gain. In a single-ended configuration,

the input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a

differential input configuration.

Figure 3 - Single-Ended Input Configuration

Receiver Section

Separation of the low and high group tones is

achieved by applying the DTMF signal to the inputs

of two sixth-order switched capacitor bandpass

filters, the bandwidths of which correspond to the low

and high group frequencies (see Fig. 7). These filters

also incorporate notches at 350 Hz and 440 Hz for

exceptional dial tone rejection. Each filter output is

followed by a single order switched capacitor filter

section which smooths the signals prior to limiting.

Limiting is performed by high-gain comparators

IN+

IN-

Ref

VOLTAGE GAIN

) = R

/ R

MT8880C/C-1

Figure 4 - Differential Input Configuration

which are provided with hysteresis to prevent

detection of unwanted low-level signals. The outputs

of the comparators provide full rail logic swings at

the frequencies of the incoming DTMF signals.

Following the filter section is a decoder employing

digital counting techniques to determine the

frequencies of the incoming tones and to verify that

they correspond to standard DTMF frequencies. A

complex averaging algorithm protects against tone

simulation by extraneous signals such as voice while

providing tolerance to small frequency deviations

and variations. This averaging algorithm has been

developed to ensure an optimum combination of

immunity to talk-off and tolerance to the presence of

interfering frequencies (third tones) and noise. When

the detector recognizes the presence of two valid

tones (this is referred to as the “signal condition” in

some industry specifications) the “Early Steering”

(ESt) output will go to an active state. Any

subsequent loss of signal condition will cause ESt to

assume an inactive state.

IN+

IN-

Ref

MT8880C/C-1

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF

R1 = R4 = R5 = 100 kΩ

R2 = 60kΩ, R3 = 37.5 kΩ

R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

diff) = R5/R1

INPUT IMPEDANCE

diff) = 2 R1

+ (1/ωC)

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